1. Field of the Invention
The present invention relates to an integrated circuit device having an insulating substrate and also a liquid crystal display device having an insulating substrate.
2. Description of the Related Art
A liquid crystal display is advantageous in that it is thin, light and is driven by a low voltage. The display is advantageous also in that it is capable of displaying color images more easily than other types of display devices. For these advantage, the liquid crystal display has recently been used in personal computers and word processors. Of the various liquid crystal displays known, an active matrix liquid crystal display having amorphous silicon thin-film transistors (a-SiTFTs) used as switching elements is particularly advantageous. Even if it has an increased number of pixels, neither contrast nor response decreases.
Amorphous silicon (a-Si) has lower carrier mobility than crystalline silicons (i.e., single crystal silicon and polycrystalline silicon). Hence, a-Si is not used in any section of a liquid crystal display, such as the drive section which needs to operate at high speed. Instead, a driving IC which has no a-SiTFTs is used as the drive section of the liquid crystal display. If incorporated in the liquid crystal display, however, the driving IC will decrease the reliability of the display and the manufacturing cost thereof.
To solve this problem, it has been proposed that an annealing method be performed on an amorphous silicon layer formed on a substrate, by applying an energy beam (e.g., a laser beam or an electron) onto selected portions of the amorphous silicon layer, thereby changing the selected portions of the layer into crystalline silicon. This method can form a drive section having crystalline silicon TFTs and a pixel section having a-SiTFTs formed monolithically--that is, on one and the same substrate. In this case, the crystalline SiTFTs of the driving section are of coplanar type, whereas the a-SiTFTs of the pixel section are of reverse stagger type more widely used than any other type of a-SiTFTs.
FIGS. 15A to 15D and FIGS. 16A to 16D are cross sectional views, explaining how the drive section and the pixel section are formed monolithically, on the same substrate. In these figures, the left half is the drive section, and the right half the pixel section.
First, as shown in FIG. 15A, an amorphous silicon film 162 is deposited on the upper surface of an insulating substrate 161. Then, a laser beam is applied onto the amorphous silicon layer, converting the layer to a crystalline (polycrystalline or single crystal) silicon film 162. Thereafter, the crystalline silicon film 162 is etched by means of photolithography, thereby removing all film 162 but that portion which will be used as a drive-section region.
Next, as illustrated in FIG. 15B, an electrode 163 is formed on the pixel-section region of the insulating substrate 161. The electrode 163 will be used as the gate electrode of a reverse stagger TFT. More specifically, a metal film is formed on the upper surface of the structure shown in FIG. 15A and is subsequently etched by photolithography, forming the gate electrode 163.
Then, as shown in FIG. 15C, a gate insulating film 164 is deposited on the upper surface of the entire structure shown in FIG. 15B. This film 164 is a component common to a coplanar TFT and a reverse stagger TFT which are to be fabricated on the substrate 161. Further, an amorphous silicon film 165 is deposited on the gate insulating film 164; the film 165 serves as the high-resistance semiconductor film of the reverse stagger TFT. An insulating film 166 is deposited on the amorphous silicon film 165; the film 166 will be processed to form the channel protective film of the reverse stagger TFT.
As shown in FIG. 15D, the insulating film 166 is etched by photolithography, forming the channel protective film of the reverse stagger TFT. An n.sup.+ amorphous silicon film 167 is deposited on the upper surface of the structure. This film 167 will serve as an ohmic contact layer of the reverse stagger TFT.
Next, as illustrated in FIG. 16A, the amorphous silicon film 165 and the n.sup.+ amorphous silicon film 167 are subjected to photolithography etching, forming films having prescribed shapes and sizes. This done, the gate insulating film 164 is etched by photolithography, making a hole (not shown) for exposing the gate electrode 163 of the reverse stagger TFT.
Then, an electrically conductive film is deposited on the upper surface of the entire structure of FIG. 16A. The conductive film is subjected to photolithography etching, thereby forming the source electrode 168 of the reverse stagger TFT, the drain electrode 169 thereof, and the gate electrode 170 of the coplanar TFT, as is illustrated in FIG. 16B. Furthermore, ions are implanted into a part of the crystalline silicon film 162, by using the gate electrode 170 as a mask. That part of the film 162 is thereby converted into a low-resistance silicon film 162a.
As shown in FIG. 16C, that portion of the n.sup.+ amorphous silicon film 167 which is located between the source electrode 168 and the drain electrode 168 is etched away, thus exposing a part of the channel protective film of the reverse stagger TFT. An insulating film (not shown) is deposited on the upper surface of the entire structure. This insulating film is subjected to photolithography etching, forming an inter-layer insulating film 171 of the coplanar TFT which functions as a driving TFT.
Next, as shown in FIG. 16D, a conductive film is deposited on the upper surface of the entire structure and etched by photolithography, forming the source electrode 172 and drain electrode 173 of the coplanar TFT. Thus, there is formed a device having a coplanar TFT and a reverse stagger TFT, both formed on the same insulating substrate 161.
This device, however, have the following problems.
First, since the gate insulating film 164 is common to a coplanar TFT and a reverse stagger TFT, both thin-film transistors cannot have a gate insulating film of an optimal thickness. This is a great design problem.
Secondly, the crystalline silicon film 162 reacts with with the metal film to be processed into the gate electrode 163, forming silicide. The silicide, thus formed, renders it no longer possible for the crystalline silicon film 162 to function as a high-resistance semiconductor film.
Thirdly, in the case where the crystalline silicon film 162 is etched by means of chemical dry etching, its surface is roughened. Hence, the gate electrode 163 formed in a later step will likely exfoliate from the insulating substrate 161, inevitably impairing the reliability of the device.
Lastly, etching scum is formed while the metal film is being etched to form the gate electrode 163. The etching scum formed causes an increase in the leak current between the coplanar TFT and the reverse stagger TFT.
The manufacturing steps shown in FIGS. 15A and 15B may be modified such that the gate electrode 163 is formed first and the crystalline silicon film 162 is formed next. In this case, there occur the following problems.
As chemical dry etching is performed on the metal film to form the gate electrode 163, the insulating substrate 161 has its surface roughened. Deposited on the rough surface of the substrate 161, the crystalline silicon film 162 has its crystallinity degraded, ultimately impairing the characteristics of the coplanar stagger TFT. Furthermore, since the gate electrode 163 is made of Mo-Ta alloy, Al or Al-Ta alloy as in devices of this type, the etching rate of the metal film for the electrode 163 cannot be much higher that that of the crystalline silicon film 162. In other words, the metal film cannot have prominent etching selectivity with respect to the crystalline silicon film 162. Thus, when the film 162 formed after the gate electrode 163 is patterned by chemical dry etching, the gate electrode 163 would be more etched than necessary.
The crystalline silicon film 162 can be etched with alkaline etching solution, not by chemical dry etchant. However, alkaline etching solution is not appropriate for use in the manufacture of semiconductor devices.